1. Field of the Invention
The present invention relates to a thin film transistor of a display panel and a method of making the same, and more particularly to a thin film transistor which can maintain the threshold voltage stability, and a method of making the above thin film transistor.
2. Description of the Prior Art
With the rapid development of display technology, there are more and more demands in the market for high resolution, low power consumption, and high performance display, so thin film transistors (TFTs) play a more important role than they did ever before. However, thin film transistors fabricated by traditional manufacturing processes often encounter reliability problems, such as poor threshold voltage stability (Vth stability). Referring to FIG. 1, FIG. 1 is a plot illustrating the relationship of the drain-to-source current (Ids) versus the gate-to-source voltage (Vgs) of the thin film transistors of a conventional LCD panel after specific deterioration conditions. As illustrated in FIG. 1, to turn off a thin film transistor normally, Ids needs to be below a threshold value (e.g. 10−9 Ampere). Several sets of different stress time are set up under specific deterioration conditions (e.g. 60° C., Vgs=−35V), and the relationship of Ids versus Vgs is measured when the drain-to-source voltage (Vds) is equal to 10V. As the stress time becomes longer (e.g. 60 seconds, 300 seconds, 600 seconds, and 1000 seconds), to let Ids be below a threshold value (e.g. 10−9 Ampere), the absolute value of Vgs has to become larger. In other words, the longer deterioration the thin film transistor goes through, the higher the absolute Vth value to overcome to turnoff the thin film transistor. I.e. it becomes less easy to turn off the thin film transistor with normal voltage, which is so-called the problem of poor threshold voltage stability.
The poor threshold voltage stability is mostly caused by the fact that between a semiconductor channel layer and a gate insulating layer there are defects or roughness on an interface in which the interface-trapped charge accumulates easily. Referring to FIG. 2, FIG. 2 is a schematic diagram illustrating a thin film transistor of a conventional LCD panel. As illustrated in FIG. 2, a thin film transistor 100 is disposed on a substrate 1 of a LCD panel. The thin film transistor 100 includes a gate electrode 2 disposed on the substrate 1, a gate insulating layer 3 disposed on the gate electrode 2 and the substrate 1, a source electrode 4 and a drain electrode 5 disposed on the gate insulating layer 3, a semiconductor channel layer 6 partially disposed on the gate insulating layer 3 between the source electrode 4 and the drain electrode 5, and partially disposed on the source electrode 4 and the drain electrode 5, and a passivation layer 7 disposed on the semiconductor channel layer 6, the source electrode 4, and the drain electrode 5. As we can see from FIG. 2, during the process of patterning a metal layer to form the source electrode 4 and the drain electrode 5, a surface of the gate insulating layer 3 will be damaged, leading to the generation of defects and roughness on the interface between the semiconductor channel layer 6 and the gate insulating layer 3, and that is the main cause of the interface-trapped charge accumulation.